Tektronix LPDDR4 Memory Bus Elec Val & Analysis Software
- Test coverage: The DDRA and DDR-LP4 Memory Validation Test solution are the most comprehensive DDR solutions supporting multiple memory standards including DDR4 and LPDDR4. User can configure custom data rate with programing custom limits to test and validate beyond the JEDEC specifications.
- Auto Configuration wizard: Easily set up the test configuration for performing electrical validation.
- Automating Read and Write Burst Separation: Tektronix provides unique Advanced Search and Mark (ASM) feature which helps to separate the Memory Read and Write burst automatically. ASM marks the memory Read and Write based on the phase relationship between the DQ and DQS automatically. This feature allows the user to perform JEDEC measurements over long record lengths. DDRA also offers other burst separation methods such as using command signals, Preamble Pattern Matching (LPDDR4/4X) methods.
- Multi-rank Memory Testing: The Visual Trigger Integration in DDRA/DDR-LP4 allows the user to quickly setup a Visual Trigger definition for an event of interest and use this definition to gate the measurements performed by DDRA/DDR-LP4.
- De-embedding: Quickly select and apply De-embedding filters from within DDRA/DDR-LP4 to de-embed the interposer and probe the effects to accurately represent the signal.
- Flexible Test Selection: Select the Memory specification and the Speed Grade for the targeted analysis.
- Cycle Type Identification: Navigate and timestamp all the acquired read and write cycles.
- Time to Test: User can perform multiple JEDEC measurements on multiple edges, multiple Read or Write bursts with a single acquisition. User can also provide statistical analysis with a single acquisition.
- Statistical Analysis: The DDRA application allows the user to capture long record lengths, identify Read and Write bursts automatically and perform multiple measurements on entire record length and perform statistical analysis.
- Debug: The DPOJET Jitter and Eye Diagram analysis tool is tightly integrated with the DDRA application which allows the user to switch between compliance and DPOJET debug tool with a single click. The debug environment uses the same setup, waveform, and measurement library like the DDRA. User can configure various parameters and plots for root cause analysis.
- Zoom the Debug word: The DDRA compliance software navigates the user to the waveform having failures in the current acquisition. This allows the user to look at the problematic part of the waveform when the test is running without saving the waveform.
- Reporting: Automatically generate comprehensive reports that include pass or fail results with the screen shots of all the measurements with cursors.
- Address/Command Bus Capture: The digital channels on the MSO5000 or MSO70000 Series Mixed Signal Oscilloscope can be used to precisely qualify the timing of different types of DDR bus cycles.
- Programmable Interface: Allows the development of remote client support for the memory test.
- Signal Access: Probing Memory BGA components is the most challenging job for most of the designers. Tektronix offers a wide range of Interposer for different Memory standards along with best in class probes to meet the Signal Integrity requirement. Tektronix solution partner Nexus provides Edge Interposer (Patented by Nexus), Socketed Interposer (Patented by Nexus), Direct Attached Interposer, and Interposer with Riser to meet the probing requirement for Memory validation.
Tektronix provides the most comprehensive solutions to serve the needs of the engineers designing DDR silicon for server, computer, graphics systems, mobile, and embedded systems, as well as those validating the physical layer compliance of DDR Memory Compliance Test Specification.
The Tektronix Option DDRA (DDR1/2/3/4, GDDR3/5, and LPDDR2/3) and LP4 (LPDDR4) includes compliance and debug solution for the following:
- DRAM components
- Data Buffer/RCD components
- System boards
- Embedded systems
- Automotive memory validation
- Graphics card memory validation
The Tektronix Option DDRA and LP4 applications includes the DDR compliance application and DDR compliance automation solution as well as the Tektronix DPOJET based DDR Jitter and Eye Diagram analysis tools for debug purposes in a single software package.
The Tektronix Option DDRA and Option LP4 applications are compatible with Tektronix DPO/MSO70000 series oscilloscopes that are designed to meet the challenges of the next generation memory standards. These oscilloscopes provide the industries leading vertical noise performance with the highest number of effective bits (ENOB) and flattest frequency response for oscilloscopes in their class.
DDRA compliance test
The Tektronix option DDRA and option LP4 automation for DDR Transmitter Compliance reduces the effort and accelerates the compliance testing for DDR systems and devices with several unique and innovative capabilities.
The DDRA configuration wizard provides a simple, step-by-step, and easy-to-use interface to speed up the testing process. The user can select the memory technology of interest, speed grade, measurement group (Read, Write, Clock, Address/Command Signal), and individual measurements within the group provides different methods of Burst detection.