Tektronix TLA7SA16 PCIe3 Logic Protocol Analyzer
Model Number: TEKTLA7SA16
The TLA7SA00 Series logic protocol analyzer modules provide an innovative approach to PCI Express validation that spans all layers of the protocol from the physical layer to the transaction layer. Feature rich software provides improved information density for viewing statistical summary and protocol analysis using innovative Transaction and Summary Profile windows. Hardware capabilities including hardware acceleration, OpenEYE, ScopePHY, and FastSYNC provide fast access to data and helps shorten the time it takes to build confidence in the test system. Powerful trigger and filtering capabilities provide the ability to quickly focus on the data of interest. A complete suite of probing solutions targeted for various form factors and applications. PCIe3 TLA7000 Logic Protocol Analyzer Module. 16 Differential Pairs (8 Lanes x8 Link Width). Two are needed for x16 requirements. Protocol and debug SW is included in the latest firmware for the TLA7012 mainframe.
- PCI Express Gen1, Gen2, and Gen3 Protocol to Physical Layer
- Analysis for link widths from x1 through x16 with up to 8.0 GT/s acquisition rates.
- Industry’s deepest 8 GB memory/module (16 GB memory, x16 link width) increases the chances of capturing an error and the fault that caused the error.
- Comprehensive PCI Express probing solutions, including midbus, slot interposer, and solder-down probes.
- Nonintrusive probing that uses OpenEYE technology incorporating automatic tuning equalization circuitry to allow probing anywhere on the channel and ensures accurate data capture in PCI Express systems with channel lengths up to 24 in. and two connectors.
- Single-click calibration process calibrates the analyzer and probes to the target BER.
- Calibration results for analyzer/probe sets are remembered from one session to another.
- ScopePHY provides the ability to quickly connect any of the PCI Express midbus, slot interposer, or solder-down probes to a high-performance oscilloscope providing a more detailed analog view of the PHY Layer.
- Shorten time to gain confidence in the test system setup.
- Front-panel LEDs provide status information such as link speed, symbol lock, and link activity.
- Auto-configure sets up the logic protocol analyzer system to be ready for data acquisition quickly.
- FastSYNC tracks the Link as it transitions in and out of ASPM Power states such as L0s, regardless of electrical Idle duration.
- Real-time statistics help observe link health and behavior over time.
- Powerful trigger-state machine spans all layers of the protocol.
- 8 States
- 8 Packet recognizers
- 4 Symbol sequence recognizers
- 4 Counter/Timers
- 4 Event flags
- Conditional storage
- Real-time filtering
- HW accelerated search and data displays provide immediate visibility of data regardless of record length.
- Information density for rapid data analysis
- The Transaction window provides visibility into protocol behavior at the packet and transaction level interspersed with physical layer activity.
- Innovative Bird’s Eye view provides a high-ground visibility of system issues involving flow control.
- The Summary Profile window helps ascertain the health of the system and identify patterns of interest such as errors, TLPs, DLLPs, ordered sets.
- Multibus visibility for system-level debug
- Analyze complete system interactions with time-correlated, multibus analysis on a single display on a single mainframe. For example, tracing memory access from PCI express to DDR memory or monitor multiple PCIe links on a PCIe switch.
- Cross Triggering and a common global time stamp enables accurate and efficient debugging by showing exactly what was happening on one bus relative to another at any given instant in time.
- 12 lb.